Ferroelectric capacitors have the advantage that they are able to switch quickly and can be fabricated on a single VLSI chip.
FeRAM's are advantageous in that they have the endurance of DRAM, the fast read/write times of SRAM and the non-volatility of flash.
Conventionally, an FeRAM is manufactured by depositing a ferroelectric film, such as lead zirconate titanate (PZT), strontium bismuth tantalum oxide (SBT), bismuth lanthanum titanium oxide (BLT) on a first, planar, electrode film, and forming a second electrode film over the ferroelectric layer. The second electrode layer and the ferroelectric film are then etched using a reactive ion etch method, after which the first electrode film is etched using a similar method. The result is a number of stacks comprising a first and second electrode film sandwiching the ferroelectric film.
In such conventional manufacturing methods, ferroelectric films are deposited on the electrode by changing deposition parameters with the aim of matching morphologies as close by as possible or any rate, promoting computability of adjacent layers. However, ferroelectric capacitors made by this method still tend to have poor characteristics, necessitating optimization of the fabrication method to minimise these problems. In order to improve ferroelectric properties, the introduction of a monolayered film prior to main ferroelectric film deposition has been reported in IFFF, 2002, Abstracts, 29B-FDI-5C, (2002), p. 49. It was shown that a PbTiO3 seed layer can act as a good crystalline buffer for PZT.
However, because the seed layer's composition and ferroelectric properties are different from those of the main PZT layer, it is difficult to exclude formation of an interfacial layer which can cause undesirable properties due to parasitic ferroelectricity and capacitance at the interface. Actually, a PbTiO3, seed layer can only form with tetragonal crystalline structure on the main PZT film. It can cause the enlargement of Vc (coercive voltage), and a large saturation voltage for ferroelectricity. In addition, further negative interface effects can be expected, since the fabrication method (Chemical Solution Deposition) for the PbTiO3 seed-layer is different from that of main PZT layer formed by sputtering.
FIG. 1 shows the hysteresis characteristics of a PZT capacitor fabricated by the conventional method. The capacitor structure is TEOS-substrate/Ti/Ir/IrO2/Pt/PZT/SRO/Pt. In this case, no seed layer was employed prior to deposition of PZT layer. The poor ferroelectric properties are due to the poor crystallinity and poor composition of the PZT films which were grown on the Pt bottom electrode (BE). The PZT film shows a depletion of Pb near the interface between the PZT film and the BE-Pt, since the element Pb can easily diffuse into the Pt bottom electrode during crystallization annealing. This strongly affects the crystallinity of the PZT film and degrades the electrical properties of PZT capacitors.